The present invention generally relates to improved methods of making flash memory devices such as EEPROMs. More particularly, the present invention relates to methods of making NAND type flash memory devices characterized by improved read disturb properties.
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1a, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one Mxc3x97N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion 11 are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG. 1b. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. A plurality of memory cells 14 connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art FIG. 1b. Each stacked gate 14c is coupled to a word line (WL0, WL1, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL0, BL1, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell 14 can be addressed for programming, reading or erasing functions.
Prior art FIG. 1c represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1a and 1b. Such a cell 14 typically includes the source 14b, the drain 14a and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxidenitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art FIG. 1b). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. 
The process for making such NAND type flash memory devices includes numerous individual processing steps, as there are numerous elements of the flash memory devices. There are numerous concerns associated with making flash memory devices that provide consistent performance and reliability. There are also numerous concerns associated with making high quality elements that constitute flash memory devices. For example, tunnel oxides are important elements since electrons tunnel therethrough during erase operations. On one hand, a relatively thick tunnel oxide results in slow erase performance. A relatively thick tunnel oxide is therefore undesirable. On the other hand, the continued trend of scaling (towards miniaturization) often undermines the ability of a tunnel oxide to handle increased amounts of electrical stress.
In particular, during electrical programming and erasing, a large amount of hot electrons are generated. Programming and erasing is often referred to as cycling. Cycling results in undesirably high levels of electron trapping in the tunnel oxide. Typically, as the number of cycles imposed on a flash memory cell increases, the number of carriers trapped in the tunnel oxide increases. Increased numbers of carriers trapped in the tunnel oxide, in turn, leads to increased erase/program times (to ensure an entire array of cells is completely charged or discharged) and/or shifts in transconductance causing charge loss. In the programmed state, defects in the tunnel oxide causes charge loss which in turn causes read disturb problems decreasing the reliability of flash memory cells. It is difficult to provide a flash memory cell capable of conducting more than about 105 program/erase cycles without showing significant read disturb problems.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality and more efficient methods of making such memory cells. In particular, flash memory cells capable of handling hot-electron stress during extended cycling are desired.
As a result of the present invention, non-volatile flash memory device fabrication is improved thereby producing devices having improved reliability. By employing the methods of the present invention which provide for specific parameters for making tunnel oxides and select gate transistor oxides, the formation of a flash memory devices characterized by reduced read disturb problems is facilitated. More specifically, the methods of the present invention minimize and/or eliminate read disturb problems in NAND type flash memory devices by minimizing and/or eliminating electron trapping in the tunnel oxide. The methods of the present invention further enable the formation of flash memory devices capable of more than about 105 program/erase cycles without significant read disturb problems.
In one embodiment, the present invention relates to a method of forming a NAND type flash memory device capable of more than about 1xc3x97105 program/erase cycles without significant read disturb problems involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
In another embodiment, the present invention relates to a method of minimizing read disturb problems in a NAND type flash memory device involving the steps of forming a first oxide layer over at least a portion of a substrate, the substrate including a core region with a flash memory cell area and a select gate area, and a periphery region with a high voltage transistor area and a low voltage transistor area; forming a nitride layer over at least a portion of the first oxide layer; removing the nitride layer and the first oxide layer from the core region of the substrate exposing the substrate in the core region; forming a second oxide layer over at least a portion of the core region of the substrate; removing a portion of the second oxide layer in the flash memory cell area of the core region of the substrate; forming a third oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the second oxide layer in the select gate area; annealing the second oxide layer and the third oxide layer in the select gate area of the core region of the substrate and the third oxide layer in the flash memory cell area of the core region of the substrate in an atmosphere comprising an inert gas and at least one of N2O and NO; depositing a first in situ doped amorphous silicon layer over at least a portion of the substrate; depositing a dielectric layer over at least a portion of the substrate; removing the dielectric layer, the first in situ doped amorphous silicon layer, the nitride layer, and the first oxide layer in the periphery region of the substrate; forming a high voltage transistor gate oxide in the high voltage transistor area of the periphery region of the substrate and low voltage transistor gate oxide in the low voltage transistor area of the periphery region of the substrate; depositing a second doped amorphous silicon layer over at least a portion of the substrate; and forming a flash memory cell in the flash memory cell area of the core region of the substrate, a select gate transistor in the select gate area of the core region of the substrate, a high voltage transistor in the high voltage transistor area of the periphery region of the substrate, and a low voltage transistor in the low voltage transistor area of the periphery region of the substrate.
In yet another embodiment, the present invention relates to a method of minimizing electron trapping in a tunnel oxide of a flash memory cell for a NAND type flash memory device, the NAND type flash memory device capable of more than about 1xc3x97105 program/erase cycles without significant read disturb problems involving the steps of forming a tunnel oxide layer having a thickness from about 50 xc3x85 to about 110 xc3x85 over at least a portion of a substrate; annealing the tunnel oxide layer in an atmosphere comprising a major amount of an inert gas and a minor amount of at least one of N2O and NO at a temperature from about 800xc2x0 C. to about 1,200xc2x0 C. for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over the tunnel oxide layer; forming a dielectric layer over the first in situ doped amorphous silicon layer; and depositing a second in situ doped amorphous silicon layer over the dielectric layer.